The present invention relates generally to flip-flop cells, and more particularly to flip-flop cells which have been designed to be modularly placed in the serial scan chain of an integrated circuit device. A serial scan chain is used as part of a serial scan test to verify the integrity of the integrated circuit after it has been fabricated. Due to the complexity of modern integrated circuitry, it is not feasible to adequately test newly fabricated devices by simply operating each device in its intended environment. It is therefore necessary to provide an efficient method of more exhaustively testing the devices after manufacture.
A serial scan test is accomplished by "daisy-chaining" all of the flip-flop cells together by connecting the output of one flip-flop cell to the input of the next flip-flop cell to form a serial scan chain. This serial scan chain operates functionally as a serial shift register. Known data is shifted serially into the flip-flop cells through this serial scan chain. Once the data is in place, the output pins of the integrated circuit are sampled and the results are compared with the expected output. If the results are not as expected, the device is known to be defective.
Typically, a flip-flop cell that is used for a serial scan chain has a test input, a data input, a test enable, and a data output line. During normal operation, the flip-flop cell receives input data from the data input line. When the integrated circuit is placed in test mode by asserting the test enable line, the flip-flop cell accepts data from the test input line.
A problem is associated with a serial scan chain built with this typical type of flip-flop cell. This problem relates to the timing specifications of the flip-flop cell. In particular, chaining successive flip-flop cells directly together often causes violations to the hold time specification of the flip-flop cell.
A flip-flop cell typically operates by transferring data on its input line to its output line whenever it senses the appropriate edge of the clock signal. Thereafter, the output line remains the same until the following clock edge. The data on the input line must be held for a period of time after the edge of the clock to ensure that the correct data is transferred to the output. This period of time is the hold time.
In the normal data path, a circuit contains combinational logic between successive flip-flops cells. This combinational logic serves to delay the time before the data on the input lines of subsequent flip-flop cells actually changes after the output of a flip-flop cell is changed. However, in the serial scan chain, the output of one flip-flop cell is connected directly to the input of the next flip-flop cell. With no additional logic between flip-flops cells to cause a delay, the input lines change almost immediately upon the arrival of the clock signal to the preceding flip-flop cell. Frequently, this causes the hold time specifications to be violated.
To remedy this problem, an additional delay element must be manually inserted after the design is completed between flip-flop cells in the serial scan chain to remove the timing violations. For large designs, the task is time-consuming and an inefficient use of resources. As the size of integrated circuitry becomes larger, it is increasingly important to have modular parts that can be inserted into a design without requiring custom fixes to clear up timing violations. Ideally, this should be done without affecting the timing of the normal data path.
Consequently, it is desirable to find an improved method of designing integrated circuits with serial scan chains by the modular placement of improved flip-flop cells which do not have hold time violations in the serial scan chain.